1. Field of the Invention
The present invention relates to methods of making chip stacks in which a plurality of integrated circuit chip packages arranged in a stack are electrically connected in a desired fashion.
2. History of the Prior Art
It is known to provide a chip stack in which a plurality of integrated circuit (IC) chips such as memory chips are formed into a stack arrangement and are electrically interconnected in desired fashion. Typically, the chips, which are included within packages therefor, have electrical contacts which are coupled in common or in parallel to contacts on a supporting substrate, as well as unique contacts which are coupled individually to the substrate to the exclusion of the other chips.
A number of different arrangements have been provided for electrically interconnecting IC chips in a stack. For example, electrical conductors which may comprise thin film metal on an insulating base may be disposed perpendicular to the planes of the planar chips so as to connect those conductors on each chip which are exposed through openings in an insulating layer. Where the chip packages are assembled into a stack, electrical connections may be accomplished by lead frames or solder strips extending along the sides of the stack and attached to the electrical contacts of the chips.
Another common technique for providing the desired electrical interconnections in a chip stack is to form a stack of chips having bonding pads disposed on the chips adjacent the outer edges thereof. After assembling the stack of chips, the chip edges are ground flat and polished before sputtering an insulating layer thereon. The bonding pads on the edges of the chips are masked during the sputtering process to avoid covering them with the insulating layer. Next, a metal layer is sputtered onto the entire edge of the stack in conjunction with photomasking which forms conductor traces of the metal layer in desired locations for connecting the bonding pads.
Still further examples of vertical stacks of IC chips and various methods of making such stacks are provided by U.S. Pat. Nos. 4,956,694, 5,313,096 and 5,612,570, which patents are commonly assigned with the present application. U.S. Pat. No. 5,612,570, which issued Mar. 18, 1997 and is entitled CHIP STACK AND METHOD OF MAKING SAME, describes a chip stack and a method for making the same in which chip packages are first assembled by mounting plastic packaged chips or thin, small outline package chips (TSOPs) within the central apertures of thin, planar frames having a thickness similar to the thickness of the packaged chip. Leads at opposite ends of the package are soldered to conductive pads on the upper surface of the surrounding frame. Each frame also has other conductive pads on the upper and lower surfaces thereof adjacent the outer edges of the frame, which are coupled to the conductive pads that receive the leads of the packaged chip by conductive traces and vias. A chip stack is then formed by stacking together a plurality of the chip packages and dipping the outer edges of the stack into molten solder to solder together the conductive pads adjacent the outer edges of the frames. The conductive pads adjacent the outer edges of the frames can be interconnected in a stair step arrangement, and pads on opposite sides of each frame can be coupled in offset fashion using vias, in order to achieve desired electrical interconnections of the various chip packages.
The chip stacks and the methods of making the same described in U.S. Pat. No. 5,612,570 have been found to be advantageous. The chip stack described therein is relatively easy to assemble using a simple process involving only a few steps. Moreover, a chip stack of relatively simple and economical configuration is provided. The stack is easily disassembled in the event that a defective chip must be replaced. Also, the design of the stack minimizes stresses occurring as a result of expansion and contraction of various materials within the stack and an attached substrate as the ambient temperature changes. The design of the stack provides the ability to electrically interconnect the chips in a manner which facilitates addressing of individual chips, such as for purposes of chip enabling as well as for common interconnection of other chip terminals.
However, it would be desirable to provide alternative methods of making chip stacks from plastic packaged or similarly packaged chips. In particular, it would be desirable to be able to make a large number of the chip stacks in simple and efficient fashion. While such chip stacks of U.S. Pat. No. 5,612,570 are relatively easy and simple to make, when compared with some of the much more complex stacks of the prior art; nevertheless, the chip stacks typically are made individually, one-at-a-time. First, each chip package is made by soldering the leads of the plastic packaged chip to the conductive pads after the chip is mounted within the frame. Then the chip packages are assembled into a stack and the edges of the stack are solder dipped in order to solder the individual chip packages together and form the stack. These steps must be repeated, over and over again, when a large number of the chip stacks are being made.
Accordingly, it would be advantageous to provide alternate methods of making chip stacks of the type described in U.S. Pat. No. 5,612,570. In particular, such methods should lend themselves to the simultaneous making of a large number of the chip stacks, so that a large number of the chip stacks may be made in a relatively speedy and efficient manner. At the same time, the methods should be capable of being carried out using industry standard processes and equipment.